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MB88346LPFV Fiches technique(PDF) 3 Page - fujitsu semiconductor |
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MB88346LPFV Fiches technique(HTML) 3 Page - fujitsu semiconductor |
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3 / 17 page ![]() MB88346L 3 ■ PIN DESCRIPTION Pin No. Symbol I/O Function 17 DI I Serial address/data input to the internal 12-bit shift register : The ad- dress/data format is that upper 4 bits (D11 to D8) indicate an address and lower 8 bits (D7 to D0) indicate data. The D11 (MSB) is the first- in bit and D0 (LSB) is the last-in bit. 14 DO O Outputs MSB bit data from 12-bit shift register. 16 CLK I Shift clock input to the internal 12-bit shift register : At the rising edge of CLK data on the DI pin is shifted into the LSB of the shift register and contents of the shift register are shifted right (to the MSB) . 15 LD I Load strobe input for a 12-bit address/data : A high level on the LD pin latches a 4-bit address (upper 4 bits : D11 to D8) of the internal 12-bit shift register into the internal address decoder, and writes 8-bit data (lower 8 bits : D7 to D0) of the shift register into an internal data latch selected by the latched address. 18 19 2 3 4 5 6 7 8 9 12 13 AO1 AO2 AO3 AO4 AO5 AO6 AO7 AO8 AO9 AO10 AO11 AO12 O 8-bit D/A output pins with OP amps. 11 VCC ⎯ MCU interface and OP amp power supply pin. 20 GND ⎯ MCU interface and OP amp ground pin. 10 VDD ⎯ D/A converter power supply pin. 1VSS ⎯ D/A converter ground pin. |
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