Micrel, Inc.

MIC706P/R/S/, MIC708R/S/T

Pin Description (Continued)

Pin Number

MIC706

Pin Number

MIC708

Pin Name

Pin Name

7

7

/RESET

signal on the manual reset input (/MR). /RESET remains asserted for one reset

timeout period (200ms) after VCC exceeds the reset threshold voltage or after the

manual reset pin transition from low to high. The watchdog timer will not assert

/RESET unless /WDO is connected to /MR.

8

N/A

/WDO

Output for the watchdog timer. The watchdog timer resets itself with each transition

to the watchdog input. If the WDI pin is held high or low for longer than the

watchdog timeout period, /WDO is forced low. /WDO will also be forced low if VCC

is below the reset threshold voltage and will remain low until VCC returns to a valid

level.

7

(MIC706P)

8

RESET

RESET is the compliment of /RESET and is asserted if either VCC goes below the

reset threshold voltage or by a low signal on the manual reset input (/MR). RESET

is suitable for microprocessor systems that use active high reset.

May 28, 2014

3

Revision 2.0