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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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IO13RSB0 Fiches technique(PDF) 14 Page - Microsemi Corporation |
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IO13RSB0 Fiches technique(HTML) 14 Page - Microsemi Corporation |
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14 / 210 page  ProASIC3 Flash Family FPGAs Re vi s i on 15 2 - 9 Table 2-13 • Summary of I/O Output Buffer Power (Per Pin) – Default I/O Software Settings 1 Applicable to Standard I/O Banks CLOAD (pF) VCCI (V) Static Power PDC3 (mW) 2 Dynamic Power PAC10 (µW/MHz) 3 Single-Ended 3.3 V LVTTL / 3.3 V LVCMOS 35 3.3 – 431.08 3.3 V LVCMOS Wide Range4 35 3.3 – 431.08 2.5 V LVCMOS 35 2.5 – 247.36 1.8 V LVCMOS 35 1.8 – 128.46 1.5 V LVCMOS (JESD8-11) 35 1.5 – 89.46 Notes: 1. Dynamic power consumption is given for standard load and software default drive strength and output slew. 2. PDC3 is the static power (where applicable) measured on VCCI. 3. PAC10 is the total dynamic power measured on VCC and VCCI. 4. All LVCMOS 3.3 V software macros support LVCMOS 3.3 V wide range as specified in the JESD8-B specification. |
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