EM73C63 datasheet(2/40 Pages) EMC

2 / 40 page

* This specification are subject to be changed without notice.

8.11.2000

EM73C63

4-BIT MICRO-CONTROLLER FOR LCD PRODUCT

Preliminary

Symbol

Pin-type

Function

Power supply (+)

Power supply (-)

RESET

RESET-A

System reset input signal, low active

mask option :

none

pull-up

CLK

OSC-C

RC or external clock source connecting pin for high speed clock source.

LXIN

OSC-B/OSC-F Crystal/RC connecting pin for low speed clock source.

LXOUT

OSC-B/OSC-F Crystal/RC connecting pin for low speed clock source.

P0(0..3)/WAKEUP0..3

INPUT-B

4-bit input port with IDLE/STOP releasing function

mask option :

wakeup enable, pull-up

wakeup enable, none

wakeup disable, pull-up

wakeup disable, pull-down

wakeup disable, none

P4.0/SOUND

I/O-O

1-bit bidirection I/O port or inverse sound effect output

mask option :

SOUND enable, push-pull, high current PMOS

SOUND disable, open-drain

SOUND disable, push-pull, high current PMOS

SOUND disable, push-pull, low current PMOS

P4(1..3)

I/O-O

3-bit bidirection I/O port with high current source.

mask option :

open-drain

push-pull, high current PMOS

push-pull, low current PMOS

P8.0(INT1)/WAKEUPA I/O-L

2-bit bidirection I/O port with external interrupt sources input and IDLE

P8.2(INT0)/WAKEUPC

/STOP releasing function

mask option :

wakeup enable, push-pull

wakeup disable, push-pull

wakeup disable, open-drain

P8.1(TRGB)/WAKEUPB I/O-L

2-bit bidirection I/O port with time/counter A,B external input and IDLE

FUNCTION BLOCK DIAGRAM

PIN DESCRIPTIONS

Interrupt

Control

Time

Base

Timer/Counter

(TA,TB)

System Control

Instruction Decoder

Instruction Register

ROM

Reset

Control

Clock

Generator

Timing

Generator

Clock Mode

Control

Data pointer

ACC

ALU

Flag

Stack pointer

Stack

RAM

I/O Control

P0.0/WAKEUP0

P0.1/WAKEUP1

P0.2/WAKEUP2

P0.3/WAKEUP3

RESET

CLK

LXOUT

SOUND GEN.

LCD Driver

Voltage

multiplier

V1~V5

VEE

LXIN

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