MAS3690CC datasheet(14/41 Pages) DYNEX

14 / 41 page

MA3690/1/3

14/41

BUS CONTROLLER MODE

For data transfers generally, 750ns enable signals

(BUFENN,R/WN etc.) are produced by the terminal with a

250ns strobe signal upon which the data will be valid.

The bus controller terminal provides signals to fetch the

message and write out a report and any associated data. The

HALTREQN and HALTEDN handshake lines operate in a

similar fasion to the BUSYREQN / BUSYACKN RT lines in that

if HALTREQN is taken low the terminal will complete the

current instruction and then halt, taking HALTEDN low to

indicate that it has done so

A BC subsystem may be operated in either a single shot or

table driven mode. In either case, the two least significant

address lines (C0,C1) to the instruction and report word stores

are provided by the terminal. On taking HALTREQN high (for a

minimum of 1us) the subsystem initiates an instruction fetch

cycle which consists of the terminal reading the instruction

word, receive command word and transmit command word

from the instruction store and transferring the data pointer

word from the instruction store to an external data address

latch. Further operation is dependent on the instruction word.

On executing a message sequence the terminal will write

out the report word and either:

1. Increment the instruction address and proceed to the

next instruction,

2. Increment the instruction address and halt,

3. Do not increment the instruction address, interrupt

subsystem and halt.

Any data associated with the command will be transferred

to or from the data store in a similar manner as used by the RT.

Figure 7: Bus Controller Subsystem Interface Signal Transfer

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