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ICS553MLF Fiches technique(PDF) 5 Page - Integrated Device Technology |
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ICS553MLF Fiches technique(HTML) 5 Page - Integrated Device Technology |
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5 / 8 page ![]() ICS553 LOW SKEW 1 TO 4 CLOCK BUFFER FAN OUT BUFFER IDT® LOW SKEW 1 TO 4 CLOCK BUFFER 5 ICS553 REV N 051310 AC Electrical Characteristics VDD = 2.5 V ±5%, Ambient Temperature -40 to +85 ° C, unless stated otherwise VDD = 3.3 V ±5%, Ambient Temperature -40 to +85 ° C, unless stated otherwise VDD = 5 V ±5%, Ambient Temperature -40 to +85 ° C, unless stated otherwise Notes: 1. With rail to rail input clock 2. Between any 2 outputs with equal loading. 3. Duty cycle on outputs will match incoming clock duty cycle. Consult IDT for tight duty cycle clock generators. Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 1.0 1.5 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 1.0 1.5 ns Propagation Delay Note 1 2.2 3 5 ns Additive Period Jitter 1 ps Output to Output Skew Note 2 Rising edges at VDD/2 0 50 ps Device to Device Skew Rising edges at VDD/2 500 ps Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 0.6 1.0 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 0.6 1.0 ns Propagation Delay Note 1 2.0 2.4 4 ns Additive Period Jitter 1 ps Output to Output Skew Note 2 Rising edges at VDD/2 0 50 ps Device to Device Skew Rising edges at VDD/2 500 ps Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency 0 200 MHz Output Rise Time tOR 0.8 to 2.0 V, CL=15 pF 0.3 0.7 ns Output Fall Time tOF 2.0 to 0.8 V, CL=15 pF 0.3 0.7 ns Propagation Delay Note 1 1.8 2.5 4 ns Additive Period Jitter 1 ps Output to Output Skew Note 2 Rising edges at VDD/2 0 50 ps Device to Device Skew Rising edges at VDD/2 500 ps |
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