ZADCS0882/0842/0822

8-Bit, 300ksps, ADC Family

Data Sheet

October 12, 2011

© 2011 Zentrum Mikroelektronik Dresden AG — Rev. 2.0

All rights reserved. The material contained herein may not be reproduced, adapted, merged, translated, stored, or used without

the prior written consent of the copyright owner. The information furnished in this publication is PRELIMINARY and subject to

changes without notice.

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Field Programmable Gate Arrays (FPGA) or Application Specific Integrated Circuits (ASIC) may use this

operation mode.

Digital Timing

In general the clock frequency at SCLK may vary from 0.1MHz to 3.3MHz. Considering all telegram pauses or

other interruptions of a continuous clock at SCLK, each conversion must be completed within 1.2ms from the

falling clock edge of the eighth bit in the Control Byte. Otherwise the signal that was captured during

sample/hold may drop to noticeable affect the conversion result. Further detailed timing information on the

digital interface is provided in Table 8 and Figure 15.

Parameter

Symbol Conditions

Min

Typ

Max

Unit

SCLK Periode

303.0

ns

SCLK Pulse Width High

151.5

ns

SCLK Pulse Width Low

151.5

ns

DIN to SCLK Setup

30

ns

DIN to SCLK Hold

10

ns

nCS Fall to SCLK Setup

30

ns

SCLK Fall to

DOUT & SSTRB Hold

10

ns

SCLK Fall to

DOUT & SSTRB Valid

40

ns

nCS Rise to

DOUT & SSTRB Disable

10

60

ns

nCS Fall to

DOUT & SSTRB Enable

60

ns

nCS Pulse Width High

100

ns

Table 8: Timing Characterisitics (VDD = +2.7V to + 5.25V;

Figure 15 Detailed Timing Diagram

nCS

SCLK

DIN

SSTRB

DOUT

t

SCL