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DS2188 Fiches technique(PDF) 8 Page - Dallas Semiconductor

No de pièce DS2188
Description  T1/CEPT Jitter Attenuator
PDF  11 Pages
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Fabricant  DALLAS [Dallas Semiconductor]
Site Internet  https://www.maximintegrated.com/en.html
Logo DALLAS - Dallas Semiconductor

DS2188 Fiches technique(HTML) 8 Page - Dallas Semiconductor

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AC ELECTRICAL CHARACTERISTICS
(0
°C to 70°C; V
DD = 5.0V ± 10%)
PARAMETER
SYMBOL
MIN
TYP
MAX
UNITS
NOTES
RCLK Period
-200
+200
ppm
1
RCLK Pulse Width
100
ns
RCLK Rise and Fall Times
50
ns
RPOS, RNEG Setup to RCLK
50
ns
RPOS, RNEG Hold for
RCLK
50
ns
Propagation delay from
RRCLK to RPOS, RRNEG
Valid
50
ns
Propagation delay from
XTAL OUT to RRCLK
50
ns
2
RST
Pulse Width
1
µA
NOTES:
1. The average period of RCLK must be within ±200 ppm of the fundamental frequency of the crystal
divided by four.
2. Only valid when the incoming jitter is less than 120 Ulpp (BDS=0) or 28 Ulpp (BDS=1).



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