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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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CS5181 Fiches technique(PDF) 14 Page - Cirrus Logic |
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CS5181 Fiches technique(HTML) 14 Page - Cirrus Logic |
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14 / 24 page  CS5181 14 DS250PP1 Power-down Mode The CS5181 has a PWDN (power-down) function. When active low, power to most of the converter’s circuitry will be reduced. If MCLK is to be stopped to save power, it should not be stopped until at least ten clock cycles after PWDN is taken low. The ten clock cycles are required to allow the part to turn off it’s internal circuitry. If the part does not get the full ten clock cycles, it will still go into a power down state, but the power dissipation could be more than is listed in the specifications for the full power down condition. When PWDN is active, the calibration information inside of the converter is maintained. When coming out of the power-down state, the converter is not recalibrated and will start-up similar to when SYNC is initiated. |
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