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CS44L10 Fiches technique(PDF) 20 Page - Cirrus Logic |
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CS44L10 Fiches technique(HTML) 20 Page - Cirrus Logic |
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20 / 34 page ![]() CS44L10 20 DS541PP1 4.9 Mode Control 2 (address 0Ah) 4.9.1 MASTER CLOCK DIVIDE ENABLE (MCLKDIV) Default = 0 Function: The MCLKDIV bit enables a circuit which divides the externally applied MCLK signal by 2 prior to all other internal circuitry. MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK require- ments. Refer to Tables 11, 12, 13, 14, and Section 6.2. 4.9.2 CLOCK DIVIDE (CLKDIV) Default = 00 Function: MCLKDIV, DBS, CLKDIV and FRQSFT are set per the user’s MCLK and LRCK requirements. Refer to Tables 11, 12, 13, 14, and Section 6.2. Σ HP_A HP_B Left Channel Audio Data Right Channel Audio Data Channel B Digital Volume Control EQ Channel A Digital Volume Control EQ & Mute & Mute Figure 5. Dynamics Control Block Diagram 76543 210 MCLKDIV CLKDV1 CLKDV0 DBS FRQSFT1 FRQSFT0 DEM1 DEM0 00000 000 |
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