UPSL100-AF5-R datasheet(5/7 Pages) UTC

5 / 7 page

UPSL100

Preliminary

LINEAR INTEGRATED CIRCUIT

UNISONICTECHNOLOGIESCO.,LTD

5 of 7

www.unisonic.com.tw

QW-R125-028.a



OPERATION DESCRIPTION(Cont.)

CS and LEB

Cycle-by-Cycle current limiting is offered in UTC UPSL100. The switch current is detected by a sense resistor into

the CS pin. An internal leading edge blanking circuit chops off the sensed voltage spike at initial power BJT on state

so that the external RC filtering on sense input is no longer needed.

Protection Control

Good power supply system reliability is achieved with its rich protection features including Cycle-by-Cycle current

limiting (OCP), VDD over voltage protection, feedback loop open protection, short circuit protection and Under

Voltage Lockout on VDD (UVLO).

Because of the coupling between secondary winding and auxiliary winding, the voltage at VDD pin will rise up if the

output of secondary side is open-circuited, when VDD pin voltage is larger than 27V, the UTC UPSL100 will stop

sending pulses to BASE pin and enter auto restart mode.

If the output of secondary side is short-circuited, the VDD voltage will drop down and the system enters under

voltage lockout protection.

Base Drive

The drive is a push pull stage with supply voltage VDD. It provides the driving current for the external power bipolar

transistor. The output signal is current limit to Is_max (typical 30mA).

UPSL100-AF5-R Fiches technique(PDF) 5 Page - Unisonic Technologies