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DSP56374 Fiches technique(PDF) 49 Page - Freescale Semiconductor, Inc |
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DSP56374 Fiches technique(HTML) 49 Page - Freescale Semiconductor, Inc |
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49 / 64 page ![]() Timer Timing DSP56374 Data Sheet, Rev. 4.2 Freescale Semiconductor 49 Figure 14. ESAI HCKT Timing Figure 15. ESAI HCKR Timing 17 Timer Timing Figure 16. TIO Timer Event Input Restrictions Table 25. Timer Timing No. Characteristics Expression 150 MHz Unit Min Max 98 TIO Low 2 × TC + 2.0 15.4 — ns 99 TIO High 2 × TC + 2.0 15.4 — ns Note: VCORE_VDD = 1.25 V ± 0.05 V; TJ = -40°C to 110°C (52 LQFP) / -40°C to 105°C (80 LQFP), CL = 50 pF HCKT SCKT (output) 96 95 Note: Figure 14 is drawn assuming positive polarity high frequency clock (THCKP=0) and positive bit clock polarity (TCKP=0). HCKR SCKR (output) 97 95 Note: Figure 15 is drawn assuming positive polarity high frequency clock (RHCKP=0) and positive bit clock polarity (RCKP=0). TIO 99 98 |
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