Pad No.

Pad Name

X

Y

Pad No.

Pad Name

X

Y

12

S4

585.25

2544.50

47

SEG24/KO14

1425.25

75.25

13

VDD1

465.25

2544.50

48

SEG25/KO15

1545.25

75.25

14

VDD2

345.25

2544.50

49

SEG26/KO16

1665.25

75.25

15

VDD3

225.25

2544.50

50

SEG27/IOD1

1785.25

75.25

16

VDD4

75.25

2544.50

51

SEG28/IOD2

1971.50

75.25

17

CUP1

75.25

2394.50

52

SEH29/IOD3/PWM1 1971.50

225.25

18

CUP2

75.25

2274.50

53

SEH30/IOD4/PWM2 1971.50

345.25

19

CUP3

75.25

2154.50

54

SEG31/IOB1/ELC

1971.50

465.25

20

COM1

75.25

2034.50

55

SEG32/IOB2/ELP

1971.50

585.25

21

COM2

75.25

1914.50

56

SEG33/IOB3/BZB

1971.50

705.25

22

COM3

75.25

1785.25

57

SEG34/IOB4/BZ

1971.50

825.25

23

COM4

75.25

1665.25

58

SEG35/IOA1/CX

1971.50

945.25

24

SEG1

75.25

1545.25

59

SEG36/IOA2/RR

1971.50

1065.25

25

SEG2

75.25

1425.25

60

SEG37/IOA3/RT

1971.50

1185.25

26

SEG3

75.25

1305.25

61

SEG38/IOA4/RH

1971.50

1305.25

27

SEG4

75.25

1185.25

62

SEG39/IOC1/KI1

1971.50

1425.25

28

SEG5

75.25

1065.25

63

SEG40/IOC2/KI2

1971.50

1545.25

29

SEG6

75.25

945.25

64

SEG41/IOC3/KI3

1971.50

1665.25

30

SEG7

75.25

825.25

65

SEG42/IOC4/KI4

1971.50

1785.25

31

SEG8

75.25

705.25

66

COM5

1971.50

1905.25

32

SEG9

75.25

585.25

67

COM6

1971.50

2034.50

33

SEG10

75.25

465.25

68

COM7

1971.50

2154.50

34

SEG11/KO1

75.25

345.25

69

COM8

1971.50

2274.50

35

SEG12/KO2

75.25

225.25

70

GND

1971.50

2394.50

Chip size : 2620 x 2050 m

Pad Descriptions

Pad Name

I/O

Description

BAK

Positive back-up voltage.

In Li mode, connects a 0.1 capacitance to GND.

VDD1

VDD2

VDD3

VDD4

LCD drive voltage and positive supply voltage.

While in Ag mode, connects +1.5V to VDD1.

While in Li/ExtV mode, connects +3.0V to VDD2.

RESET

I

Input pin for LSI reset signal.

With Internal pull-down resistor.

INT

I

Input pin for external INT request signal.

Falling edge or rising edge triggered by mask option.

Internal pull-down or pull-up resistor or floatting to be selected by mask option.

TESTA I Test signal input pin, internal pull-down resistor.

TESTA

I

Test signal input pin.

CUP1

CUP2

CUP3

O

Switching pins for supplying the LCD driving voltage to the VDD1, 2, 3, 4 pins.

Connects the CUP1, CUP2 and CUP3 pins with a nonpolarized electronic

capacitor if 1/2, 1/3 or 1/4 bias mode has been selected. In the STATIC mode,

these pins should be open.

Preliminary

3

Ver. 0.0