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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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AD9549APCBZ Fiches technique(PDF) 47 Page - Analog Devices |
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AD9549APCBZ Fiches technique(HTML) 47 Page - Analog Devices |
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47 / 76 page  AD9549 Rev. D | Page 47 of 76 CSB SCLK SDIO tHI tLO tCLK tS tDS tDH tH BIT N BIT N + 1 Figure 58. Serial Control Port Timing—Write Table 12. Definitions of Terms Used in Serial Control Port Timing Diagrams Parameter Description t CLK Period of SCLK t DV Read data valid time (time from falling edge of SCLK to valid data on SDIO/SDO) t DS Setup time between data and rising edge of SCLK t DH Hold time between data and rising edge of SCLK t S Setup time between CSB and SCLK t H Hold time between CSB and SCLK t HI Minimum period that SCLK should be in a logic high state t LO Minimum period that SCLK should be in a logic low state |
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