ACPL-331J datasheet(21/23 Pages) AVAGO

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Figure 35. Output pull-down resistor.

DESAT Pin Protection Resistor

The freewheeling of flyback diodes connected across

the IGBTs can have large instantaneous forward voltage

transients which greatly exceed the nominal forward

voltage of the diode. This may result in a large negative

voltage spike on the DESAT pin which will draw substan-

tial current out of the driver if protection is not used. To

limit this current to levels that will not damage the driver

IC, a 100 ohm resistor should be inserted in series with

the DESAT diode. The added resistance will not alter the

DESAT threshold or the DESAT blanking time.

Figure 36. DESAT pin protection.

VLED

DESAT

VCC2

VEE

VOUT

VCLAMP

VEE

VCC1

FAULT

CATHODE

ANODE

CATHODE

RPULL-DOWN

VCC

VLED

DESAT

VCC2

VEE

VOUT

VCLAMP

VEE

VCC1

FAULT

CATHODE

ANODE

CATHODE

RPULL-DOWN

VCC

VLED

DESAT

VCC2

VEE

VOUT

VCLAMP

VEE

VCC1

FAULT

CATHODE

ANODE

CATHODE

VCC

100 Ω

100pF

DDESAT

VCC

Under Voltage Lockout

The ACPL-331J Under Voltage Lockout (UVLO) feature is

designed to prevent the application of insufficient gate

voltage to the IGBT by forcing the ACPL-331J output

low during power-up. IGBTs typically require gate

voltages of 15 V to achieve their rated VCE(ON) voltage.

At gate voltages below 13 V typically, the VCE(ON) voltage

increases dramatically, especially at higher currents. At

very low gate voltages (below 10 V), the IGBT may operate

in the linear region and quickly overheat. The UVLO

function causes the output to be clamped whenever in-

sufficient operating supply (VCC2) is applied. Once VCC2

exceeds VUVLO+ (the positive-going UVLO threshold), the

UVLO clamp is released to allow the device output to turn

on in response to input signals. As VCC2 is increased from

0 V (at some level below VUVLO+), first the DESAT protec-

tion circuitry becomes active. As VCC2 is further increased

(above VUVLO+), the UVLO clamp is released. Before the

time the UVLO clamp is released, the DESAT protection

is already active. Therefore, the UVLO and DESAT Fault

detection feature work together to provide seamless pro-

tection regardless of supply voltage (VCC2).

Active Miller Clamp

A Miller clamp allows the control of the Miller current

during a high dV/dt situation and can eliminate the use

of a negative supply voltage in most of the applications.

During turn-off, the gate voltage is monitored and the

clamp output is activated when gate voltage goes below

2V (relative to VEE). The clamp voltage is VOL+2.5V typ

for a Miller current up to 1100mA. The clamp is disabled

when the LED input is triggered again.

Other Recommended Components

The application circuit in Figure 33 includes an output

pull-down resistor, a DESAT pin protection resistor, a

FAULT pin capacitor, and a FAULT pin pullup resistor and

Active Miller Clamp connection.

Output Pull-Down Resistor

During the output high transition, the output voltage

rapidly rises to within 3 diode drops of VCC2. If the output

current then drops to zero due to a capacitive load, the

output voltage will slowly rise from roughly VCC2-3(VBE)

to VCC2 within a period of several microseconds. To limit

the output voltage to VCC2-3(VBE), a pull-down resistor,

RPULL-DOWN between the output and VEE is recommended

to sink a static current of several 650 µA while the output

is high. Pull-down resistor values are dependent on the

amount of positive supply and can be adjusted according

to the formula, Rpull-down = [VCC2-3 * (VBE)] / 650 µA.

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