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74HC595D Fiches technique(PDF) 13 Page - NXP Semiconductors |
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74HC595D Fiches technique(HTML) 13 Page - NXP Semiconductors |
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13 / 24 page ![]() 74HC_HCT595 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved. Product data sheet Rev. 6 — 12 December 2011 13 of 24 NXP Semiconductors 74HC595; 74HCT595 8-bit serial-in, serial or parallel-out shift register with output latches; 3-state Measurement points are given in Table 8. VOL and VOH are typical output voltage levels that occur with the output load. Fig 10. Storage clock to output propagation delays mna558 ST CP input Qn output tPLH tPHL tW tsu 1/fmax VM VOH VI GND VOL VM SH CP input VI GND VM Measurement points are given in Table 8. The shaded areas indicate when the input is permitted to change for predictable output performance. VOL and VOH are typical output voltage levels that occur with the output load. Fig 11. Data set-up and hold times mna560 GND GND th tsu th tsu VM VM VM VI VOH VOL VI Q 7S output SH CP input DS input |
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