Low-Jitter, Low-Noise LVDS

Repeater in an SC70 Package

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7

Figure 1. LVDS Fail-Safe Input

OUT+

IN+

IN-

OUT-

Figure 2. DC Load Test Circuit

1.25V

IN+

IN-

1.20V

1.25V

1.20V

OUT-

OUT+

Figure 3. Transition Time and Propagation Delay Test Circuit

PULSE

GENERATOR

IN+

IN-

50

Ω

50

Ω

OUT-

OUT+

Test Circuit and Timing Diagrams