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L7980 Fiches technique(PDF) 25 Page - STMicroelectronics |
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L7980 Fiches technique(HTML) 25 Page - STMicroelectronics |
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25 / 44 page ![]() L7980 Application informations Doc ID 15181 Rev 4 25/44 Figure 14. Open loop gain: module bode diagram The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow: 1. Choose a value for R1, usually between 1 kΩ and 5 kΩ, in order to have values of C4 and C5 not comparable with parasitic capacitance of the board. 2. Choose a gain (R4/R1) in order to have the required bandwidth (BW), that means: Equation 25 Where fESR is the ESR zero: Equation 26 and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant. 3. Calculate C4 by placing the zero one decade below the output filter double pole: Equation 27 4. Then calculate C3 in order to place the second pole at four times the system bandwidth (BW): R 4 f ESR f LC ------------ ⎝⎠ ⎛⎞ 2 BW f ESR ------------ V S V IN --------- R 1 ⋅⋅ ⋅ = f ESR 1 2 π ESR C OUT ⋅⋅ -------------------------------------------- = C 4 10 2 π R 4 f LC ⋅⋅ ------------------------------- = |
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