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DSPIC33FJ12GP201TE/ML Fiches technique(PDF) 14 Page - Microchip Technology |
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DSPIC33FJ12GP201TE/ML Fiches technique(HTML) 14 Page - Microchip Technology |
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14 / 242 page ![]() dsPIC33FJ12GP201/202 DS70264B-page 12 Preliminary © 2007 Microchip Technology Inc. FIGURE 2-1: dsPIC33FJ12GP201/202 CPU CORE BLOCK DIAGRAM Instruction Decode & Control PCH PCL Program Counter 16-bit ALU 24 23 Instruction Reg PCU 16 x 16 W Register Array ROM Latch EA MUX Interrupt Controller Stack Control Logic Loop Control Logic Data Latch Address Latch Control Signals to Various Blocks Address Bus 16 16 16 To Peripheral Modules Data Latch Address Latch 16 X RAM Y RAM Address Generator Units 16 Y Data Bus X Data Bus DSP Engine Divide Support 16 16 23 23 16 8 PSV & Table Data Access Control Block 16 16 16 16 Program Memory Data Latch Address Latch |
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