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23LCV1024-IP Fiches technique(PDF) 11 Page - Microchip Technology

No de pièce 23LCV1024-IP
Description  1 Mbit SPI Serial SRAM with Battery Backup and SDI Interface
PDF  30 Pages
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Fabricant  MICROCHIP [Microchip Technology]
Site Internet  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

23LCV1024-IP Fiches technique(HTML) 11 Page - Microchip Technology

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 2012 Microchip Technology Inc.
Preliminary
DS25156A-page 11
23LCV1024
2.6
Write Mode Register Instruction
(WRMR)
The Write Mode Register instruction (WRMR) allows the
user to write to the bits in the MODE register as shown
in Table 2-2. This allows for setting of the Device
operating mode. Several of the bits in the MODE
register must be cleared to ‘0’. See Figure 2-8 for the
WRMR timing sequence.
FIGURE 2-8:
WRITE MODE REGISTER TIMING SEQUENCE (WRMR)
2.7
Power-On State
The 23LCV1024 powers on in the following state:
• The device is in low-power Standby mode
(CS = 1)
• A high-to-low-level transition on CS is required to
enter active state
SO
SI
CS
9
1011
12131415
01
0
0
0
0
00
76
5
4
21
0
Instruction
Data to MODE Register
High-Impedance
SCK
0
2
34
56
7
18
3



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