L99MC6 datasheet(31/55 Pages) STMICROELECTRONICS

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L99MC6

Functional description of the SPI

Doc ID 16523 Rev 1

31/55

The <Global Error Flag> is generated by an OR-combination of all failure events of the

device (that is <Global Status Register>, [0:6]).

Figure 13. Indication of the global error flag on DO when CSN is low and SCK is stable

The last transferred SPI command is still valid in the input shift register. If SCK is stable (high or low) during a CSN low

pulse, at the rising edge of CSN the last transferred SPI command is still valid in the input shift register and is repeated.

Therefore, it is recommended to send a complete SPI frame to monitor the status of the L99MC6.

Writing to the selected data input register is only enabled if exactly one frame length is

transmitted within one communication frame (that is CSN low). If more or less clock pulses

are counted within one frame, the complete frame is ignored and a SPI frame error is

signaled in the Global Status register. This safety function is implemented to avoid

an unwanted activation of output stages by a wrong communication frame.

Communication error

Active high

Bit is set if the number of clock cycles during

CSN = low does not match with the specified

frame width or if an invalid bus condition is

detected (DI always 1).

DI always 0 automatically leads to clearing the

enable bit in CTRL0 and is not signaled as

communication error.

Global Error flag

Active high

Logic OR combination of all failures in the

<Global Status Byte>.

Table 17.

Global status register description (continued)

Bit

Description

Polarity

Comment

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