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STM8AF6126 Fiches technique(PDF) 64 Page - STMicroelectronics |
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STM8AF6126 Fiches technique(HTML) 64 Page - STMicroelectronics |
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64 / 89 page ![]() Electrical characteristics STM8AF61xx, STM8AF62xx 64/89 Doc ID 14952 Rev 6 Figure 34. Typical NRST pull-up resistance RPU vs VDD Figure 35. Typical NRST pull-up current Ipu vs VDD The reset network shown in Figure 36 protects the device against parasitic resets. The user must ensure that the level on the NRST pin can go below VIL(NRST) max (see Table 38: NRST pin characteristics ), otherwise the reset is not taken into account internally. Figure 36. Recommended reset pin protection 30 35 40 45 50 55 60 2.5 3 3.5 4 4.5 5 5.5 6 V DD [V] -40°C 25°C 85°C 125°C 0 20 40 60 80 100 120 140 01 2 3 4 5 6 V DD [V] -40°C 25°C 85°C 125°C External reset circuit STM8A Filter RPU VDD Internal reset NRST 0.1µF (optional) |
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