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M68HC08 Fiches technique(PDF) 83 Page - Freescale Semiconductor, Inc

No de pièce M68HC08
Description  MC68HC908JB16 Technical Data
PDF  332 Pages
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Fabricant  FREESCALE [Freescale Semiconductor, Inc]
Site Internet  http://www.freescale.com
Logo FREESCALE - Freescale Semiconductor, Inc

M68HC08 Fiches technique(HTML) 83 Page - Freescale Semiconductor, Inc

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Central Processor Unit (CPU)
MC68HC908JB16 — Rev. 1.1
Technical Data
Freescale Semiconductor
Central Processor Unit (CPU)
83
6.6.2 Stop Mode
The STOP instruction:
•
Clears the interrupt mask (I bit) in the condition code register,
enabling external interrupts. After exit from stop mode by external
interrupt, the I bit remains clear. After exit by reset, the I bit is set.
•
Disables the CPU clock.
After exiting stop mode, the CPU clock begins running after the oscillator
stabilization delay.
6.7 CPU During Break Interrupts
If the break module is enabled, a break interrupt causes the CPU to
execute the software interrupt instruction (SWI) at the completion of the
current CPU instruction. (See Section 19. Break Module (BRK).) The
program counter vectors to $FFFC–$FFFD ($FEFC–$FEFD in monitor
mode).
A return-from-interrupt instruction (RTI) in the break routine ends the
break interrupt and returns the MCU to normal operation if the break
interrupt has been deasserted.
6.8 Instruction Set Summary
Table 6-1 provides a summary of the M68HC08 instruction set.
6.9 Opcode Map
The opcode map is provided in Table 6-2.



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