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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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ST7FLITE25F2M6 Fiches technique(PDF) 55 Page - STMicroelectronics |
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ST7FLITE25F2M6 Fiches technique(HTML) 55 Page - STMicroelectronics |
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55 / 166 page  ST7LITE20F2 ST7LITE25F2 ST7LITE29F2 Power saving modes Doc ID 8349 Rev 5 55/166 ones which get their clock supply from another clock generator (such as an external or auxiliary oscillator). The compatibility of Watchdog operation with HALT mode is configured by the “WDGHALT” option bit of the option byte. The HALT instruction when executed while the Watchdog system is enabled, can generate a Watchdog RESET (see Section 15.1: Option bytes for more details). Figure 24. HALT timing overview HALT Run Run 256 or 4096 CPU cycle delay Reset or interrupt HALT instruction Fetch vector [ACTIVE-HALT disabled] |
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