ICS83021I datasheet(7/12 Pages) IDT

No de pièce	ICS83021I

Description	1-TO-1 DIFFERENTIAL- TO-LVCMOS/LVTTL TRANSLATOR

PDF	12 Pages

Scroll/Zoom	100%

Fabricant	IDT [Integrated Device Technology]

Site Internet	http://www.idt.com

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ICS83021I

1-TO-1 DIFFERENTIAL-TO-LVCMOS/LVTTL TRANSLATOR

IDT™ / ICS™ LVCMOS/LVTTL TRANSLATOR

ICS83031AMI REV. C OCTOBER 31, 2008

Parameter Measurement Information, continued

Propagation Delay

Output Duty Cycle/Pulse Width/Period

Application Information

Wiring the Differential Input to Accept Single Ended Levels

Figure 1 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF = VDD/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio of

R1 and R2 might need to be adjusted to position the V_REF in the

center of the input voltage swing. For example, if the input clock

swing is only 2.5V and VDD = 3.3V, V_REF should be 1.25V and

R2/R1 = 0.609.

Figure 1. Single-Ended Signal Driving Differential Input

nCLK

CLK

PERIOD

odc =

x 100%

V_REF

Single Ended Clock Input

VDD

CLK

nCLK

0.1u

ICS83021I Fiches technique(PDF) 7 Page - Integrated Device Technology