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ICS574MLFT Fiches technique(PDF) 4 Page - Integrated Device Technology |
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ICS574MLFT Fiches technique(HTML) 4 Page - Integrated Device Technology |
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4 / 7 page ![]() ICS574 ZERO DELAY, LOW SKEW BUFFER ZDB IDT™/ ICS™ ZERO DELAY, LOW SKEW BUFFER 4 ICS574 REV G 051310 DC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature -40 to +85 ° C AC Electrical Characteristics Unless stated otherwise, VDD = 3.3 V, Ambient Temperature -40 to +85 ° C Notes: 1. Stresses beyond those listed in Absolute Maximum Ratings can permanently damage the device. Prolonged exposure to levels above the operating limits but below the Absolute Maximum Ratings may affect device reliability. 2. With CLKIN = 160 MHz, FBIN to CLK4. Using Spread Spectrum Input Clocks The ICS574 uses IDT’s Spread Smart technology, allowing it to accurately track (pass through) any clocks that implement spread spectrum techniques. Parameter Symbol Conditions Min. Typ. Max. Units Operating Supply Voltage VDD 3 5.5 V Input High Voltage VIH VDD/2+1 V Input Low Voltage VIL VDD/2-1 V Output High Voltage, CMOS level VOH IOH = -5 mA VDD-0.4 V Output High Voltage VOH IOH = -18 mA 2.4 V Output Low Voltage VOL IOL = 18 mA 0.4 V IDD Operating Supply Current No load (Note 2) 36 mA Short Circuit Current IOS Each output ±65 mA Input Capacitance CIN 7pF Parameter Symbol Conditions Min. Typ. Max. Units Input Frequency, clock fIN FBIN from CLK4 20 160 MHz Output Frequency, clock FBIN from CLK4 20 160 MHz Output Clock Rise Time 0.8 to 2.0 V, 15 pF load 1.5 ns Output Clock Fall Time 2.0 to 0.8 V, 15 pF load 1.5 ns Output Clock Duty Cycle, 3.3 V At 1.4 V 40 50 60 % Device-to-device Skew, equally loaded Rising edges at VDD/2 700 ps Outpu-to-output Skew, equally loaded Rising edges at VDD/2 150 ps Maximum Absolute Jitter 170 ps Cycle-to-cycle Jitter, 15 pF loads 66.67 MHz outputs 250 ps |
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