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ADM7160AUJZ-2.5-R2 Fiches technique(PDF) 21 Page - Analog Devices |
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ADM7160AUJZ-2.5-R2 Fiches technique(HTML) 21 Page - Analog Devices |
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21 / 24 page ![]() Data Sheet ADM7160 Rev. 0 | Page 21 of 24 OUTLINE DIMENSIONS *COMPLIANT TO JEDEC STANDARDS MO-193-AB WITH THE EXCEPTION OF PACKAGE HEIGHT AND THICKNESS. 1.60 BSC 2.80 BSC 1.90 BSC 0.95 BSC 0.20 0.08 0.60 0.45 0.30 8° 4° 0° 0.50 0.30 0.10 MAX *1.00 MAX *0.90 MAX 0.70 MIN 2.90 BSC 5 4 1 2 3 SEATING PLANE Figure 61. 5-Lead Thin Small Outline Transistor Package [TSOT] (UJ-5) Dimensions shown in millimeters 1.70 1.60 1.50 0.425 0.350 0.275 TOP VIEW 6 1 4 3 0.35 0.30 0.25 BOTTOM VIEW PIN 1 INDEX AREA SEATING PLANE 0.60 0.55 0.50 1.10 1.00 0.90 0.20 REF 0.05 MAX 0.02 NOM 0.65 BSC EXPOSED PAD PIN 1 INDICATOR (R 0.15) FOR PROPER CONNECTION OF THE EXPOSED PAD, REFER TO THE PIN CONFIGURATION AND FUNCTION DESCRIPTIONS SECTION OF THIS DATA SHEET. 0.15 REF 2.10 2.00 SQ 1.90 0.20 MIN Figure 62. 6-Lead Lead Frame Chip Scale Package [LFCSP_UD] 2.00 mm × 2.00 mm Body, Ultra Thin, Dual Lead (CP-6-3) Dimensions shown in millimeters |
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