ICS85320AMILF datasheet(7/16 Pages) IDT

7 / 16 page

IDT™ / ICS™ 3.3V, 2.5V LVPECL TRANSLATOR

ICS8532AMI REV A NOVEMBER 13, 2006

ICS85320I

LVCMOS/LVTTL-TO-DIFFERENTIAL 3.3V, 2.5V LVPECL TRANSLATOR

APPLICATION INFORMATION

CC - 2V

Ω

RTT

o = 50Ω

FOUT

FIN

RTT =

((V

OH + VOL) / (VCC – 2)) – 2

3.3V

125

Ω

125

Ω

o = 50Ω

FOUT

FIN

The clock layout topology shown below is a typical termination

for LVPECL outputs. The two different layouts mentioned are

recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that gen-

erate ECL/LVPECL compatible outputs. Therefore, terminating

resistors (DC current path to ground) or current sources must be

used for functionality. These outputs are designed to drive 50

Ω

transmission lines. Matched impedance techniques should be

used to maximize operating frequency and minimize signal dis-

tortion.

Figures 1A and 1B show two different layouts which are

recommended only as guidelines. Other suitable clock layouts

may exist and it would be recommended that the board design-

ers simulate to guarantee compatibility across all printed circuit

and clock component process variations.

TERMINATION FOR LVPECL OUTPUTS

FIGURE 1B. LVPECL OUTPUT TERMINATION

FIGURE 1A. LVPECL OUTPUT TERMINATION

ICS85320AMILF Fiches technique(PDF) 7 Page - Integrated Device Technology