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EP610DM/B Fiches technique(PDF) 8 Page - Rochester Electronics

No de pièce EP610DM/B
Description  High-performance, 16-macrocell Classic EPLD Pipelined data rates of up to 100 MHz
PDF  9 Pages
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Fabricant  ROCHESTER [Rochester Electronics]
Site Internet  http://www.rocelec.com/
Logo ROCHESTER - Rochester Electronics

EP610DM/B Fiches technique(HTML) 8 Page - Rochester Electronics

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EP610
Specification Number EP610-CI (AT) REV -
Page 8 of 9
AC Operating Conditions: EP610-XX/B Note (1)
Symbol
Parameter
Conditions
Min
Max
Unit
tPD1
Input to non-registered output
C1 = 35 pF Notes (2), (3)
35
ns
tPD2
I/O input to non-registered output
37
ns
tPZX
Input to output enable
35
ns
tPXZ
Input to output disable
C1 = 5 pF Notes (2), (3), (4), (5)
35
ns
tCLR
Asynchronous output clear time
C1 = 35 pF Notes (2), (3)
37
ns
fMAX
Maximum clock frequency
Note (2), (6), (7)
37.0
MHz
tSU
Global clock input setup time
Note (2), (3)
27
ns
tH
Global clock input hold time
Note (3)
0
ns
tCH
Global clock high time
Note (4)
12
ns
tCL
Global clock low time
Note (4)
12
ns
tCO1
Global clock to output delay
20
ns
tCNT
Global clock minimum period
Note (4), (8)
35
ns
fCNT
Global clock internal maximum frequency
Note (8)
28.5
MHz
tASU
Array clock input setup time
Notes (2), (3), (4)
8
ns
tAH
Array clock input hold time
Notes (2), (3), (4)
12
ns
tACH
Array clock high time
Notes (3), (4)
12
ns
tACL
Array clock low time
Notes (3), (4)
12
ns
tACO1
Array clock to output delay
Notes (2), (3)
37
ns
tACNT
Array clock minimum period
Notes (4), (8)
35
ns
fACNT
Array clock internal maximum frequency
Notes (4), (8)
28.6
MHz
Notes to tables:
(1) Screening and characterization of AC delay parameters are conducted at 10 MHz or less.
Operating conditions: VCC = 5 V ± 10%, TC = -55° C to 125° C for military use.
(2) All array-dependent delays are specified for an XOR pattern. This pattern includes two product terms and two
pure inputs; all other product terms in the macrocell are held low by one EPROM cell. Other patterns may result
in longer delays. Delays for patterns involving only one product term (such as tPXZ ) are specified for an XOR
pattern in which only one pure input switches at a time.
(3) When the Turbo Bit is not set (non-turbo mode), a non-turbo adder of 30 ns (maximum) is added to this
parameter to determine worst-case timing. Parameters may not be tested in non-turbo mode, but are
guaranteed to the limits specified. Devices operating in non-turbo mode require one input or I/O transition to
guarantee that the device will enter the correct power-up state.
(4) These parameters may not be tested, but are guaranteed to the limits specified in the table under “Absolute
Maximum Ratings” on page 3.
(5) Not tested directly, but guaranteed by testing tPD.
(6) The fMAX values represent the highest frequency for pipelined data.
(7) Not tested directly, but derived from tSU.
(8) Specified with device programmed as a 16-bit counter with no output loading.



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