TIMING SOLUTIONS

11

MOTOROLA

The Following Figures Illustrate the Measurement Reference for the MPC9600 Clock Driver Circuit

Figure 11. CCLK MPC9600 AC test reference

Figure 12. PCLK MPC9600 AC test reference

Pulse

Generator

Z = 50

W

RT = 50 Ω

ZO = 50 Ω

RT = 50 Ω

ZO = 50 Ω

MPC9600 DUT

VTT

VTT

Differential

Pulse Generator

Z = 50

W

RT = 50 Ω

ZO = 50 Ω

RT = 50 Ω

ZO = 50 Ω

MPC9600 DUT

VTT

VTT

offset) test reference

Figure 15. Output Duty Cycle (DC)

Figure 16. Output–to–output Skew tSK(O)

The pin–to–pin skew is defined as the worst case difference in

propagation delay between any similar delay path within a

single device

The time from the PLL controlled edge to the non controlled

edge, divided by the time between PLL controlled edges,

expressed as a percentage

VCC

VCCB2

GND

VCC

VCCB2

GND

tSK(O)

VCC

VCCB2

GND

tP

T0

DC = tP/T0 x 100%

VCC

VCCB2

GND

VCC

VCCB2

GND

t(

∅)

CCLK

FB_IN

VCC

VCCB2

GND

t(

∅)

PCLK

FB_IN

PCLK

VPP

VCMR

Freescale Semiconductor, Inc.

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