CY62156ESL datasheet(9/16 Pages) CYPRESS

9 / 16 page

CY62156ESL MoBL®

Document Number: 001-54995 Rev. *D

Page 9 of 16

Figure 6. Write Cycle No 1: WE Controlled [20, 21, 22]

Figure 7. Write Cycle 2: CE Controlled [20, 21, 22]

Switching Waveforms (continued)

tHD

tSD

tPWE

tSA

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

NOTE 23

CE1

ADDRESS

CE2

DATA I/O

BHE/BLE

tHD

tSD

tPWE

tHA

tAW

tSCE

tWC

tHZOE

VALID DATA

tBW

tSA

NOTE 23

CE1

ADDRESS

CE2

DATA I/O

BHE/BLE

Notes

20. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, BHE, BLE or both = VIL, and CE2 = VIH. All signals must be active to initiate a write

and any of these signals can terminate a write by going inactive. The data input setup and hold timing must be referenced to the edge of the signal that terminates the

write.

21. Data I/O is high impedance if OE = VIH.

22. If CE1 goes HIGH and CE2 goes LOW simultaneously with WE = VIH, the output remains in a high impedance state.

23. During this period, the I/Os are in output state. Do not apply input signals.

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