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CY7C1327G Fiches technique(PDF) 15 Page - Cypress Semiconductor

No de pièce CY7C1327G
Description  4-Mbit (256 K x 18) Pipelined Sync SRAM
PDF  23 Pages
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Fabricant  CYPRESS [Cypress Semiconductor]
Site Internet  http://www.cypress.com
Logo CYPRESS - Cypress Semiconductor

CY7C1327G Fiches technique(HTML) 15 Page - Cypress Semiconductor

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CY7C1327G
Document Number: 38-05519 Rev. *M
Page 15 of 23
Figure 5. Read/Write Cycle Timing [21, 22, 23]
Switching Waveforms (continued)
tCYC
tCL
CLK
ADSP
tADH
tADS
ADDRESS
tCH
OE
ADSC
CE
tAH
tAS
A2
tCEH
tCES
BWE,
BW [A:B]
Data Out (Q)
High-Z
ADV
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
Data In (D)
BURST READ
Back-to-Back READs
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWEH
tWES
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
tCLZ
tCO
Back-to-Back
WRITEs
A1
DON’T CARE
UNDEFINED
A3
Notes
21. On this diagram, when CE is LOW: CE1 is LOW, CE2 is HIGH and CE3 is LOW. When CE is HIGH: CE1 is HIGH or CE2 is LOW or CE3 is HIGH.
22. The data bus (Q) remains in high Z following a WRITE cycle, unless a new read access is initiated by ADSP or ADSC.
23. GW is HIGH.



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