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MPC875CVR133 Fiches technique(PDF) 27 Page - Freescale Semiconductor, Inc |
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MPC875CVR133 Fiches technique(HTML) 27 Page - Freescale Semiconductor, Inc |
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27 / 84 page ![]() MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 27 Bus Signal Timing Figure 9 provides the timing for the synchronous input signals. Figure 9. Synchronous Input Signals Timing Figure 10 provides normal case timing for input data. It also applies to normal read accesses under the control of the user-programmable machine (UPM) in the memory controller. Figure 10. Input Data Timing in Normal Case CLKOUT TA, BI TEA, KR, RETRY, CR BB, BG, BR B16 B17 B16a B17a B16b B17 CLKOUT TA D[0:31] B16 B17 B19 B18 |
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