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LP3876ES-ADJ/NOPB Fiches technique(PDF) 2 Page - Texas Instruments |
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LP3876ES-ADJ/NOPB Fiches technique(HTML) 2 Page - Texas Instruments |
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2 / 19 page ![]() LP3876-ADJ SNVS245C – SEPTEMBER 2003 – REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. CONNECTION DIAGRAM Figure 1. TO-220-5 Package (Top View) Figure 2. DDPAK/TO-263-5 Package (Top View) Bent, Staggered Leads Table 1. PIN DESCRIPTION for TO-220-5 and DDPAK/TO-263-5 Packages LP3876-ADJ Pin # Name Function 1 SD Shutdown 2 VIN Input Supply 3 GND Ground 4 VOUT Output Voltage 5 ADJ Set Output Voltage BLOCK DIAGRAM LP3876-ADJ 2 Submit Documentation Feedback Copyright © 2003–2013, Texas Instruments Incorporated Product Folder Links: LP3876-ADJ |
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