ADE7763ARSZRL datasheet(52/56 Pages) AD

52 / 56 page

ADE7763

Data Sheet

Rev. C | Page 52 of 56

Bit

Location

Bit

Mnemonic

Default

Value

Description

14, 13

WAVSEL1, 0

Use these bits to select the source of the sampled data for the waveform register.

WAVSEL1, 0

Length

Source

24 bits, active power signal (output of LPF2)

Reserved

24 bits, Channel 1

24 bits, Channel 2

POAM

Writing Logic 1 to this bit allows only positive active power to accumulate. The default value of this

bit is 0.

SWAP

(SWAP CH1 AND CH2 ADCs)

DTRT

(WAVEFORM SAMPLES OUTPUT DATA RATE)

00 = 27.9kSPS (CLKIN/128)

01 = 14.4kSPS (CLKIN/256)

10 = 7.2kSPS (CLKIN/512)

11 = 3.6kSPS (CLKIN/1024)

POAM

(POSITIVE ONLY ACCUMULATION)

WAVSEL

(WAVEFORM SELECTION FOR SAMPLE MODE)

00 = LPF2

01 = RESERVED

10 = CH1

11 = CH2

15 14 13 12 11 10

ADDR: 0x09

DISHPF

(DISABLE HPF1 IN CHANNEL 1)

DISLPF2

(DISABLE LPF2 AFTER MULTIPLIER)

DISCF

(DISABLE FREQUENCY OUTPUT CF)

DISSAG

(DISABLE SAG OUTPUT)

ASUSPEND

(SUSPEND CH1 AND CH2 ADCs)

TEMPSEL

(START TEMPERATURE SENSING)

SWRST

(SOFTWARE CHIP RESET)

CYCMODE

(LINE CYCLE ENERGY ACCUMULATION MODE)

DISCH2

(SHORT THE ANALOG INPUTS ON CHANNEL 2)

DISCH1

(SHORT THE ANALOG INPUTS ON CHANNEL 1)

NOTE: REGISTER CONTENTS SHOW POWER-ON DEFAULTS

Figure 86. Mode Register

ADE7763ARSZRL Fiches technique(PDF) 52 Page - Analog Devices

ADE7763ARSZRL Fiches technique(HTML) 52 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56

Fiches technique Télécharger

Lien URL