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Moteur de recherche de fiches techniques de composants électroniques |
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Moteur de recherche de fiches techniques de composants électroniques |
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LCMXO2-640ZE-2TG100C Fiches technique(PDF) 84 Page - Lattice Semiconductor |
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LCMXO2-640ZE-2TG100C Fiches technique(HTML) 84 Page - Lattice Semiconductor |
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84 / 106 page  4-8 Pinout Information MachXO2 Family Data Sheet For Further Information For further information regarding logic signal connections for various packages please refer to the MachXO2 Device Pinout Files. Thermal Management Thermal management is recommended as part of any sound FPGA design methodology. To assess the thermal characteristics of a system, Lattice specifies a maximum allowable junction temperature in all device data sheets. Users must complete a thermal analysis of their specific design to ensure that the device and package do not exceed the junction temperature limits. Refer to the Thermal Management document to find the device/package specific thermal values. For Further Information For further information regarding Thermal Management, refer to the following: • Thermal Management document • TN1198, Power Estimation and Management for MachXO2 Devices • The Power Calculator tool is included with the Lattice design tools, or as a standalone download from www.latticesemi.com/software |
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