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OP471GS Fiches technique(PDF) 14 Page - Analog Devices |
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OP471GS Fiches technique(HTML) 14 Page - Analog Devices |
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14 / 16 page ![]() REV. A OP471 –14– OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 14-Lead PDIP Package (N-14) 14 1 7 8 PIN 1 0.795 (20.19) 0.725 (18.42) 0.280 (7.11) 0.240 (6.10) 0.100 (2.54) BSC SEATING PLANE 0.060 (1.52) 0.015 (0.38) 0.210 (5.33) MAX 0.022 (0.558) 0.014 (0.356) 0.160 (4.06) 0.115 (2.93) 0.070 (1.77) 0.045 (1.15) 0.130 (3.30) MIN 0.195 (4.95) 0.115 (2.93) 0.015 (0.381) 0.008 (0.204) 0.325 (8.25) 0.300 (7.62) 14-Lead CERDIP Package (Q-14) 14 17 8 0.310 (7.87) 0.220 (5.59) PIN 1 0.005 (0.13) MIN 0.098 (2.49) MAX 0.100 (2.54) BSC 15 0 0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20) SEATING PLANE 0.200 (5.08) MAX 0.785 (19.94) MAX 0.150 (3.81) MIN 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36) 0.070 (1.78) 0.030 (0.76) 0.060 (1.52) 0.015 (0.38) 16-Lead SOIC Package (R-16) SEATING PLANE 0.0118 (0.30) 0.0040 (0.10) 0.0192 (0.49) 0.0138 (0.35) 0.1043 (2.65) 0.0926 (2.35) 0.050 (1.27) BSC 16 9 8 1 0.4193 (10.65) 0.3937 (10.00) 0.2992 (7.60) 0.2914 (7.40) PIN 1 0.4133 (10.50) 0.3977 (10.00) 0.0125 (0.32) 0.0091 (0.23) 8 0 0.0291 (0.74) 0.0098 (0.25) 45 0.0500 (1.27) 0.0157 (0.40) |
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