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DAC8426 Fiches technique(PDF) 8 Page - Analog Devices |
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DAC8426 Fiches technique(HTML) 8 Page - Analog Devices |
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8 / 12 page ![]() DAC8426 –8– REV. C a) Large Signal b) Settling Time Response (Negative Transition) c) Settling Time Response (Positive Transition) Figure 3. Dynamic Response The outputs can withstand an indefinite short-circuit to AGND to typically 50 mA. The output may also be shorted to any volt- age between VDD and VSS; however, care must be taken to not exceed the device maximum power dissipation. The amplifier’s emitter follower output stage consists of an in- trinsic NPN bipolar transistor with a 400 µA NMOS pull-down current-source load connected to VSS. This circuit configuration shown in Figure 4 enables the output amplifier to develop out- put voltages very close to AGND. Only the negative supply of the four output buffer amplifiers are connected to VSS. Operating the DAC8426 from dual supplies (VDD = +15 V and VSS = –5 V) improves negative going output settling time near zero volts. When operating single supply (VDD = +15 V and VSS = 0 V) the output sink current decreases as the output approaches zero voltage. Within 200 mV of AGND (single-supply operation) the internal sinking capability appears resistive at a value of approxi- mately 1200 Ω. The buffer amplifier output current and voltage characteristics are plotted in Figure 5. Test Conditions, All Photos: VDD = +15 V CREFOUT = 10 F RL = 2 k Digital Input Sequence 0, 255, 0 |
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