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ADV601

–47–

REV. 0

Host Interface (Compressed Data) Register Timing

The diagrams in this section show transfer timing for host read and write transfers to the ADV601’s Compressed Data register. Ac-

cesses to the Compressed Data register are faster than access timing for the Indirect Address, Indirect Register Data, and Interrupt

Mask/Status registers. For information on access timing for the other registers, see the Host Interface (Indirect Address, Indirect

RD or WR

signal assertion timing, your system does NOT have to wait for the

ACK signal between new compressed data addresses.

Table XXXV. Host (Compressed Data) Read Timing Parameters

Parameter

Description

Min

Max

Unit

tRD_CD_RDC

RD Signal, Compressed Data Direct Register, Read Cycle Time

N/A

tRD_CD_PWA

RD Signal, Compressed Data Direct Register, Pulse Width Asserted

N/A

tRD_CD_PWD

RD Signal, Compressed Data Direct Register, Pulse Width Deasserted

N/A

tADR_CD_RDS

ADR Bus, Compressed Data Direct Register, Read Setup

N/A

tADR_CD_RDH

ADR Bus, Compressed Data Direct Register, Read Hold (at 27 MHz VCLK)

N/A

tDATA_CD_RDD

DATA Bus, Compressed Data Direct Register, Read Delay

N/A

tDATA_CD_RDOH

DATA Bus, Compressed Data Direct Register, Read Output Hold

N/A

tACK_CD_RDD

ACK Signal, Compressed Data Direct Register, Read Delay

N/A

tACK_CD_RDOH

ACK Signal, Compressed Data Direct Register, Read Output Hold

N/A

(I) ADR,

BE, CS

(I)

(O) DATA

(O)

ACK

VALID

ADR_CD_RDS

DATA_CD_RDD

ACK_CD_RDD

ACK_CD_RDOH

DATA_CD_RDOH

ADR_CD_RDH

RD_CD_RDC

RD_CD_PWA

RD_CD_PWD

Figure 39. Host (Compressed Data) Read Transfer Timing

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