AD9849 datasheet(6/36 Pages) AD

6 / 36 page

REV. 0

–6–

AD9848/AD9849

TIMING SPECIFICATIONS

(CL = 20 pF, fCLI = 20 MHz [AD9848] or 30 MHz [AD9849], Serial Timing in Figure 3, unless

otherwise noted.)

Parameter

Symbol

Min

Typ

Max

Unit

MASTER CLOCK (CLI), AD9848

CLI Clock Period

tCLI

CLI High/Low Pulsewidth

tADC

Delay From CLI to Internal Pixel Period Position

tCLIDLY

6ns

MASTER CLOCK (CLI), AD9849

CLI Clock Period

tCONV

33.33

CLI High/Low Pulsewidth

tADC

16.67

EXTERNAL MODE CLAMPING

CLPDM Pulsewidth

tCDM

Pixels

CLPOB Pulsewidth

tCOB

Pixels

SAMPLE CLOCKS

SHP Rising Edge to SHD Rising Edge (AD9848)

tS1

SHP Rising Edge to SHD Rising Edge (AD9849)

tS1

DATA OUTPUTS

Output Delay from Programmed Edge

tOD

6ns

Pipeline Delay

Cycles

SERIAL INTERFACE

Maximum SCK Frequency

fSCLK

MHz

SL to SCK Setup Time

tLS

SCK to SL Hold Time

tLH

SDATA Valid to SCK Rising Edge Setup

tDS

SCK Falling Edge to SDATA Valid Hold

tDH

SCK Falling Edge to SDATA Valid Read

tDV

NOTES

1Maximum CLPOB pulsewidth is for functional operation only. Wider typical pulses are recommended to achieve low noise clamp reference.

Specifications subject to change without notice.

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