AD8600AP datasheet(6/16 Pages) AD

6 / 16 page

REV. 0

–6–

AD8600

TRANSFER EQUATIONS

Output Voltage

i = D ×

REF

256

where i is the DAC channel number and D is the decimal value

of the DAC register data.

Table I. Truth Table

R/W

CS LD

Operation

Write to DAC Register

–

Update DAC Register

–

Update DAC Register

Latches DAC Register

DAC Register Transparent

Write to Input Register

Load Data to Input Register at

Decoded Address

Latches Data in Input Register at

Decoded Address

Latches Data in Input Register at

Decoded Address

Readback Input Registers

Input Register Readback (Data

Access)

Hi-Z Readback Disconnects from

Bus

Hi-Z on Data Bus

Reset

Clear All Registers to Zero,

VOUT = 0 V

Latches All Registers to Zero

= Low; Input Register Ready

for R/W, DAC Register Latched

to Zero

NOTES

1+ symbol means positive edge of control input line.

2– symbol means negative edge of control input line.

Decoded DAC Register

i = A

where A is the decimal value of the decoded address bits A3,

A2, A1, A0 (LSB).

Address, CS, R/W and data inputs should be stable prior to acti-

vation of the active low EN input. Input registers are transpar-

ent when EN is low. When EN returns high, data is latched into

the decoded input register. When the load strobe LD and EN

pins are active low, all input register data is transferred to the

DAC registers. The DAC registers are transparent while they

are enabled.

Table II. Address Decode Table

Addr

DAC

(MSB)

(LSB)

Code

Updated

(Binary)

(Hex)

000

001

010

011

100

101

O10

101

O11

110

O12

110

O13

111

O14

111

O15

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