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AD5516 Fiches technique(PDF) 13 Page - Analog Devices |
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AD5516 Fiches technique(HTML) 13 Page - Analog Devices |
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13 / 16 page ![]() REV. 0 AD5516 –13– APPLICATION CIRCUITS The AD5516 is suited for use in many applications, such as level setting, optical, industrial systems, and automatic test applica- tions. In level setting and servo applications where a fine-tune adjust is required, the Mode 2 function increases resolution. The following figures show the AD5516 used in some potential applications. AD5516 in a Typical ATE System The AD5516 is ideally suited for the level setting function in automatic test equipment. A number of DACs are required to control pin drivers, comparators, active loads, parametric mea- surement units, and signal timing. Figure 10 shows the AD5516 in such a system. DAC STORED DATA AND INHIBIT PATTERN PERIOD GENERATION AND DELAY TIMING DACs FORMATTER COMPARE REGISTER SYSTEM BUS DAC DAC DAC DAC ACTIVE LOAD PARAMETRIC MEASUREMENT UNIT SYSTEM BUS DAC DAC COMPARATOR DUT DRIVER Figure 10. AD5516 in an ATE System AD5516 in an Optical Network Control Loop The AD5516 can be used in optical network control applica- tions that require a large number of DACs to perform a control and measurement function. In the example shown below, the outputs of the AD5516 are fed into amplifiers and used to control actuators that determine the position of MEMS mirrors in an optical switch. The exact position of each mirror is measured and the readings are multiplexed into an 8-channel, 14-bit ADC (AD7865). The increment and decrement modes of the DACs are useful in this application as it allows the user 14-bit resolution. The control loop is driven by an ADSP-2106x, a 32-bit SHARC DSP. AD5516 0 15 MEMS MIRROR ARRAY 0 15 S E N S O R S ADG609 2 0 7 AD7865 AD8644 2 ADSP-2106x Figure 11. AD5516 in an Optical Control Loop POWER SUPPLY DECOUPLING In any circuit where accuracy is important, careful consideration of the power supply and ground return layout helps to ensure the rated performance. The printed circuit board on which the AD5516 is mounted should be designed so that the analog and digital sections are separated and confined to certain areas of the board. If the AD5516 is in a system where multiple devices require an AGND-to-DGND connection, the connection should be made at one point only. The star ground point should be established as close as possible to the device. For supplies with multiple pins (AVCC1, AVCC2) it is recommended to tie those pins together. The AD5516 should have ample supply bypassing of 10 µF in parallel with 0.1 µF on each supply located as closely to the package as possible, ideally right up against the device. The 10 µF capacitors are the tantalum bead type. The 0.1 µF capacitor should have low effective series resistance (ESR) and effective series inductance (ESI), like the common ceramic types that provide a low-impedance path to ground at high frequencies, to handle transient currents due to internal logic switching. The power supply lines of the AD5516 should use as large a trace as possible to provide low-impedance paths and reduce the effects of glitches on the power supply line. Fast switching signals such as clocks should be shielded with digital ground to avoid radiating noise to other parts of the board, and should never be run near the reference inputs. A ground line routed between the DIN and SCLK lines will help reduce crosstalk between them (not required on a multilayer board as there will be a separate ground plane, but separating the lines will help). It is essential to minimize noise on REFIN. Avoid crossover of digital and analog signals. Traces on opposite sides of the board should run at right angles to each other. This reduces the effects of feedthrough through the board. A micro- strip technique is by far the best, but not always possible with a double-sided board. In this technique, the component side of the board is dedicated to ground plane while signal traces are placed on the solder side. As is the case for all thin packages, care must be taken to avoid flexing the package and to avoid a point load on the surface of the package during the assembly process. |
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