RT9502 datasheet(12/13 Pages) RICHTEK

12 / 13 page

RT9502

DS9502-02 April 2011

www.richtek.com

Temperature Regulation and Thermal Protection

In order to maximize the charge rate, the RT9502 features

a junction temperature regulation loop. If the power

dissipation of the IC results in a junction temperature

greater than the thermal regulation threshold (125

°C), the

RT9502 throttles back on the charge current in order to

maintain a junction temperature around the thermal

regulation threshold (125

°C). The RT9502 monitors the

junction temperature, TJ, of the die and disconnects the

battery from the input if TJ exceeds 125

°C. This operation

continues until junction temperature falls below thermal

regulation threshold (125

°C) by the hysteresis level. This

feature prevents the chip from damage.

Selecting the Input and Output Capacitors

In most applications, the most important is the high-

frequency decoupling capacitor on the input of the RT9502.

A 1uF ceramic capacitor, placed in close proximity to input

pin and GND pin is recommended. In some applications

depending on the power supply characteristics and cable

length, it may be necessary to add an additional 10uF

ceramic capacitor to the input. The RT9502 requires a

small output capacitor for loop stability. A 1uF ceramic

capacitor placed between the BATT pin and GND is typically

sufficient.

Layout Consideration

The RT9502 is a fully integrated low cost single-cell Li-

Ion battery charger ideal for portable applications. Careful

PCB layout is necessary. For best performance, place all

peripheral components as close to the IC as possible. A

short connection is highly recommended. The following

guidelines should be strictly followed when designing a

PCB layout for the RT9502.

Input capacitor should be placed close to IC and

connected to ground plane. The trace of input in the

PCB should be placed far away the sensitive devices or

shielded by the ground.

The GND should be connected to a strong ground plane

for heat sinking and noise protection.

The connection of RSETA should be isolated from other

noisy traces. The short wire is recommended to prevent

EMI and noise coupling.

Figure 5

GND

ACIN

USB

GND

CHG_S

PGOOD

BATT

ISETA

ISETU

RSETA

Battery

GND

The capacitor should be

placed close to IC pin and

connected to ground plane.

The GND should be connected to a

strong ground plane for heat sinking

and noise protection.

The connection of RSETA should be

isolated from other noisy traces.

The short wire is recommended to

prevent EMI and noise coupling.

The TS's capacitor should be

placed close to TS(Pin 9) and

connected to ground plane.

The capacitance (0.1uF to

10uF) base on PCB layout.

When PCB has poor layout

the 10uF is recommended to

prevent noise.

Output capacitor should be placed close to IC and

connected to ground plane to reduce noise coupling.

The TS's capacitor should be placed close to TS (Pin 9)

and connected to ground plane. The capacitance (0.1uF

to 10uF) base on PCB layout. When PCB has poor

layout, the 10uF is recommended to prevent noise.

RT9502 Fiches technique(PDF) 12 Page - Richtek Technology Corporation

RT9502 Fiches technique(HTML) 12 Page - Richtek Technology Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13

Fiches technique Télécharger

Lien URL