Features

PXD10 Product Brief, Rev. 1

Freescale Semiconductor

21

•

Unique 9-bit vector for each of the possible 128 separate interrupt sources

•

Eight software-triggerable interrupt sources

•

16 priority levels with fixed hardware arbitration within priority levels for each interrupt source

•

Ability to modify the ISR or task priority.

— Modifying the priority can be used to implement the Priority Ceiling Protocol for accessing

shared resources.

•

External non-maskable interrupt directly accessing the main core critical interrupt mechanism

•

32 external interrupts

2.4.24

System Integration Unit (SIU)

The SIU controls MCU reset configuration, pad configuration, external interrupt, general purpose I/O

(GPIO), internal peripheral multiplexing, and the system reset operation.

The GPIO features the following:

•

Up to 4 levels of internal pin multiplexing, allowing exceptional flexibility in the allocation of

device functions for each package

•

Centralized general purpose input output (GPIO) control of up to 132 input/output pins (package

dependent)

•

All GPIO pins can be independently configured to support pull-up, pull down, or no pull

•

Reading and writing to GPIO supported both as individual pins and 16-bit wide ports

•

All peripheral pins can be alternatively configured as both general purpose input or output pins

except ADC channels which support alternative configuration as general purpose inputs

•

Direct readback of the pin value supported on all digital output pins through the SIU

•

Configurable digital input filter that can be applied to up to 14 general purpose input pins for noise

elimination on external interrupts

•

Register configuration protected against change with soft lock for temporary guard or hard lock to

prevent modification until next reset.

2.4.25

System Clocks and Clock Generation Modules

The system clock on the PXD10 can be derived from an external oscillator, an on-chip FMPLL, or the

internal 16 MHz oscillator.

•

The source system clock frequency can be changed via an on-chip programmable clock divider (

1

to

2).

•

Additional programmable peripheral bus clock divider ratio (

1 to 16)

•

The PXD10 has 2 on-chip FMPLLs—the primary module and an auxiliary module.

— Each features the following:

– Input clock frequency from 4 MHz to 16 MHz

– Lock detect circuitry continuously monitors lock status

– Loss Of Clock (LOC) detection for reference and feedback clocks