EMIF06-SD03F3

Data transmission

Doc ID 15194 Rev 2

11/23

Figure 7.

4.1

Test circuit from host to SD

Test circuit from host to SD is shown in Figure 8. Timings are measured for the whole line

card capacitance 10 pF).

Figure 8.

Test circuit from host to SD

Table 11.

1.

Symbol

Parameter

Test conditions

Min. Typ. Max. Unit

Propagation delay hl from host to SD

Section 4.1

-3.5

6

ns

Propagation delay lh from host to SD

-

3.5

6

Propagation delay hl from SD to host

Section 4.2

-3

6

ns

Propagation delay lh from SD to host

-

3

6

Rise time from host to SD

Section 4.1

-1.5

3

ns

Rise time from SD to host

Section 4.2

-0.5

2

Fall time from host to SD

Section 4.1

-1.9

3

ns

Fall time from SD to host

Section 4.2

-0.5

2

Delay differences from host to SD

Section 4.1,Section 4.3

-1.0

0

1.0

ns

Section 4.2, Section 4.4

-1.5

0

1.5

ns

Propagation delay for CLK feedback

-

6.5

12

ns

Rise time for CLK feedback

Section 4.2

-0.5

2

ns

Fall time for CLK feedback

Section 4.2

-0.5

2

ns

INPUT

0V

0V

Vor V

ccA

ccB

Vor V

ccA

ccB

OUTPUT

70%

20%

20%

50%

50%

50%

50%

tplh

tr

tf

tphl

70%

HOST

SD

Csd =15 pF