STLC3075_09 datasheet(18/36 Pages) STMICROELECTRONICS

No de pièce	STLC3075

Description	Integrated POTS interface for home access gateway and WLL

PDF	36 Pages

Scroll/Zoom	100%

Fabricant	STMICROELECTRONICS [STMicroelectronics]

Site Internet	http://www.st.com

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18 / 36 page

Application information

STLC3075

18/36

CVPOS should be defined depending on the power supply current capability and maximum allowable ripple

For low ripple application use 2x47m F in parallel.

Can be saved if proper PCB layout avoid noise coupling on RD pin (high impedance input).

RF1 sets the self generated battery voltage in RING and ACTIVE(Il=0) mode as shown in Table 11.

VBATR should be defined considering the ring peak level required (Vringpeak=VBATR - 6 V typ.). This relation is valid

providing that the VPOS power supply current capability and the RSENSE programming allow to source all the current

requested by the particular ringer load configuration

For high efficiency in HI-Z mode coil resistance @125kHz must be < 3

Ω.

Table 11.

VBAT values in RING and ACTIVE modes

267k

280k

294k

300k

VBAT (ACTIVE)

-46V

-48V

-49V

-50V

VBATR (RING)

-62V

-65V

-68V

-70V

STLC3075 Fiches technique(PDF) 18 Page - STMicroelectronics