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SPIRIT1 Fiches technique(PDF) 68 Page - STMicroelectronics |
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SPIRIT1 Fiches technique(HTML) 68 Page - STMicroelectronics |
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68 / 94 page ![]() MCU interface SPIRIT1 68/94 Doc ID 022758 Rev 3 10.2 Interrupts In order to notify the MCU of a certain number of events an interrupt signal is generated on a selectable GPIO. The following events trigger an interrupt to the MCU: All interrupts are reported on a set of interrupt status registers and are individually maskable. The interrupt status register must be cleared upon a read event from the MCU. The status of all the interrupts is reported on the IRQ_STATUS[3:0] registers: bits are high for the events that have generated any interrupts. The interrupts are individually maskable Table 32. Interrupts Bit Events group Interrupt event 0 Packet oriented RX data ready 1 RX data discarded (upon filtering) 2TX data sent 3 Max. re-TX reached 4 CRC error 5 TX FIFO underflow/overflow error 6 RX FIFO underflow/overflow error 7 TX FIFO almost full 8 TX FIFO almost empty 9 RX FIFO almost full 10 RX FIFO almost empty 11 Max. number of backoff during CCA 12 Signal quality related Valid preamble detected 13 Sync word detected 14 RSSI above threshold (carrier sense) 15 Device status related Wake-up timeout in LDCR mode(1) 1. The interrupt flag n.15 is set (and consequently the interrupt request) only when the XO clock is available for the state machine. This time may be delayed compared to the actual timer expiration. However, the real time event can be sensed putting the end-of-counting signal on a GPIO output. 16 READY(2) 2. The interrupt flag n.16 is set each time the SPIRIT1 goes to READY state and the XO has completed its setting transient (XO ready condition detected). 17 STANDBY state switching in progress 18 Low battery level 19 Power-on reset 20 Brownout event 21 LOCK 29 Timer related RX operation timeout 30 Others AES end–of–operation |
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