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SN74ACT2236 Fiches technique(PDF) 9 Page - Texas Instruments

No de pièce SN74ACT2236
Description  1024x9x2 ASYNCHRONOUS BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY
PDF  14 Pages
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Fabricant  TI1 [Texas Instruments]
Site Internet  http://www.ti.com
Logo TI1 - Texas Instruments

SN74ACT2236 Fiches technique(HTML) 9 Page - Texas Instruments

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SN74ACT2236
1024 × 9 × 2
ASYNCHRONOUS BIDIRECTIONAL FIRST IN, FIRST OUT MEMORY
SCAS149A − APRIL 1990 − REVISED SEPTEMBER 1995
9
POST OFFICE BOX 655303
• DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
electrical characteristics over recommended operating free-air temperature range (unless
otherwise noted)
PARAMETER
TEST CONDITIONS
MIN
TYP†
MAX
UNIT
VOH
VCC = 4.5 V,
IOH = − 8 mA
2.4
V
VOL
Flags
VCC = 4.5 V,
IOL = 8 mA
0.5
V
VOL
I/O ports
VCC = 4.5 V,
IOL = 16 mA
0.5
V
II
VCC = 5.5 V,
VI = VCC or 0
±5
µA
IOZ
VCC = 5.5 V,
VO = VCC or 0
±5
µA
ICC‡
VI = VCC − 0.2 V or 0
10
400
µA
∆ICC§
DIR, OE
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
2
mA
∆ICC§
Other inputs
VCC = 5.5 V,
One input at 3.4 V,
Other inputs at VCC or GND
1
mA
Ci
VI = 0,
f = 1 MHz
4
pF
Co
VO = 0,
f = 1 MHz
8
pF
† All typical values are at VCC = 5 V, TA = 25°C.
‡ ICC tested with outputs open.
§ This is the supply current when each input is at one of the specified TTL voltage levels rather than 0 V or VCC.
switching characteristics over recommended ranges of supply voltage and operating free-air
temperature, CL = 50 pF (unless otherwise noted) (see Figures 4 and 5)
PARAMETER
FROM
TO
′ACT2236-20
′ACT2236-30
′ACT2236-40
′ACT2236-60
UNIT
PARAMETER
FROM
(INPUT)
TO
(OUTPUT)
MIN
TYP†
MAX
MIN
MAX
MIN
MAX
MIN
MAX
UNIT
fmax
LDCK
50
33
25
16.7
MHz
fmax
UNCK
50
33
25
16.7
MHz
tpd
LDCK
↑, LDCKB↑
B or A
8
23
8
23
8
25
8
27
ns
tpd
UNCKA
↑,
UNCKB
↑
B or A
10
17
25
10
25
10
35
10
45
ns
tPLH
LDCK
↑, LDCKB↑
EMPTYA,
EMPTYB
4
15
4
15
4
17
4
19
ns
tPHL
UNCKA
↑,
UNCKB
↑
EMPTYA,
EMPTYB
2
17
2
17
2
19
2
21
ns
tPHL
RSTA
↓, RSTB↓
EMPTYA,
EMPTYB
2
18
2
18
2
20
2
22
ns
tPHL
LDCK
↑, LDCKB↑
FULLA, FULLB
4
15
4
15
4
17
4
19
ns
tPLH
UNCKA
↑,
UNCKB
↑
FULLA, FULLB
4
15
4
15
4
17
4
19
ns
tPLH
RSTA
↓, RSTB↓
FULLA, FULLB
2
15
2
15
2
17
2
19
ns
tPLH
RSTA
↓, RSTB↓
AF/AEA, AF/AEB
2
15
2
15
2
17
2
19
ns
tPLH
LDCK
↑, LDCKB↑
HFA, HFB
2
15
2
15
2
17
2
19
ns
tPHL
UNCKA
↑,
UNCKB
↑
HFA, HFB
4
19
4
19
4
21
4
23
ns
tPHL
RSTA
↓, RSTB↓
HFA, HFB
1
15
1
15
1
17
1
19
ns
tpd
SAB or SBA¶
B or A
1
11
1
11
1
13
1
15
ns
tpd
A or B
B or A
1
11
1
11
1
13
1
15
ns
tpd
LDCK
↑, LDCKB↑ AF/AEA, AF/AEB
2
19
2
19
2
21
2
23
ns
tpd
UNCKA
↑,
UNCKB
↑
AF/AEA, AF/AEB
2
19
2
19
2
23
2
23
ns
ten
DIR, OE
A or B
2
12
2
12
2
14
2
16
ns
tdis
DIR, OE
A or B
1
10
1
10
1
12
1
14
ns
† All typical values are at VCC = 5 V, TA = 25°C.
¶ These parameters are measured with the internal output state of the storage register opposite to that of the bus input.



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