ThunderLAN

™ TNETE110A

PCI ETHERNET

™ CONTROLLER

SINGLE-CHIP 10 BASE-T

SPWS022A – APRIL 1996 – REVISED NOVEMBER 1996

21

POST OFFICE BOX 1443

MIN

TYP

MAX

UNIT

td(VDDH – FXTL1V)

Delay time from minimum VDD high level to first valid FXTL1V full swing period

100‡

ms

tw(H)

Pulse duration at FXTL1 high

13‡

ns

tw(L)

Pulse duration at FXTL1 low

13‡

ns

tt

Transition time of FXTL1

7

ns

tc

Cycle time, FXTL1

50

ns

Tolerance of FXTL1 input frequency

"0.01

%

† The FXTL signal may be implemented by either connecting a 20-MHz crystal across the FXTL1 and FXTL2 pins or by driving the FXTL1 from

a 20-MHz crystal oscillator module.

‡ This specification is provided as an aid to board design. This specification is not tested during manufacturing testing.

FXTL1

VDD

td(VDDH – FXTL1V)

Minimum VDD High Level

tc

tw(H)

tw(L)

tt

tt

Figure 9. Crystal Oscillator Timing