TNETX15VE datasheet(100/113 Pages) TI1

100 / 113 page

TNETX15VE

VLAN-ENGINE ADDRESS-LOOKUP DEVICE

SPWS028B – APRIL 1997 – REVISED SEPTEMBER 1997

100

POST OFFICE BOX 655303

• DALLAS, TEXAS 75265

timing requirements

OSCIN clock

MIN

NOM

MAX

UNIT

tc(OSCIN)

Cycle time, OSCIN

tw(OSCINH)

Pulse duration, OSCIN high

tw(OSCINL)

Pulse duration, OSCIN low

Frequency drift, OSCIN clock

±50

ppm

timing requirements (see Figure 25)

power-on reset

NO.

MIN

MAX

UNIT

td(RESET)1

Delay time, from VCC↑ to RESET↑

td(RESET)2

Delay time, from OSCIN

↑ to RESET↑

td(AUTO)

Delay time, from RESET

↑ to EEPROM autoload finished

OSCIN

(input)

VCC(5V)

(input)

VCC

(input)

RESET

(input)

Normal Operation

Signals†

Valid

† Outputs are floated during reset. Inputs and I/O’s that are not connected to a known logic state at all times, including reset, should have a pullup

or pulldown resistor.

Figure 25. Power-On Reset Timing

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